This invention relates to a method and an apparatus for effectively reading out a picture image information in accordance with an operation cycle consisting of photeolectric conversion, accumulation, transference, storage and read-out steps in use of a solid state image pick-up device.
Recently, image sensors have been widely improved with the development of the solid state device mainly containing an integrated circuit. However, it may be said that these image sensors have not yet fully satisfied various requirements, and accordingly, many attempts have been paid to devices or equipments to which such image sensors are to be applied. Thus, a picture image information read-out device becomes itself complicated and expensive.
FIG. 1 is a block diagram representing a circuit system generally utilized on these days for reading out picture images by means of a solid state image pick-up tube and shows a case in which an image sensorconsisting of a charge coupled device (CCD) is utilized as a solid state image pick-up element and the image information is synchronized with a clock signal CK at an image unit 2 and subjected to photoelectric conversion (IA), and thereafter, the converted information is transferred (TA) into a storage unit 3. An electric charge pattern once stored in the storage unit 3 is transferred by a standard scanning method or system and then read out (RA) from a read-out register 4 as a picture image signal (PS). The cycle consisting of these steps of photoelectric conversion (IA), transference (TA), storage and read-out (RA) is evenly controlled by the clock signal CK provided with predetermined frequencies and generated from a clock signal generating circuit 1 and the timings of the generations of the clock signal CK from the clock signal generating circuit 1 are shown in FIG. 2.
Referring to FIG. 2, under the timing of the clock signal CK, upon a time t1 when the photoelectric conversion (IA) and the transference (TA) have been completed as steps of the picture image read-out cycle of an image of a picture image G1, an accumulated image information (G1) is read out and the next read-out cycle of the next picture image G2 is started. Likewise, upon a time t2 when the transference and the storage of the image information of the picture image G2 have been completed, the accumulated image information (G2) is read out (RA) and the next read-out cycle of the next picture image G3 is started. These read-out cycles are sequentially continued with the similar manner.
As a frequency of the clock signal CK for controlling each read-out cycle is required a relatively high frequency of several hundreds KHz to several MHz, and in case this frequency is low, a dark current may adversely increase and smear may be generated because the accumulated time and transferring time are elongated, thus resulting in degradation in quality of the image data. For the reason described before, a quick speed performance is required for these peripheral circuit elements, and the solid state image pickup device of this type becomes expensive.
Namely, when the frequency of the clock signal being drive signal of the image sensor is lowered, the dark current is adversely increased and the smear also occurs thereby to degrade the quality of a product, and inversely, when the frequency of the clock signal is increased for preventing the degradation of the quality thereof, the image signal is outputted at a speed in response to the thus increased high frequency, which requires a sampled-and -hold circuit for obtaining the matching between the speed of image processing of the system and the same of the image signal and also requires a high-speed analog to digital (A/D) converter.